1. FIELD OF THE INVENTION
This invention relates to semiconductor circuits and more specifically to a buffer circuit for interconnecting a CMOS logic and a TTL circuit logic.
2. INTRODUCTION
In CMOS circuits there is a familiar problem of connecting CMOS logic circuits to operate with binary logic signals from TTL logic circuits. From a more general standpoint, there is a problem in connecting a CMOS circuit to operate with signals in a different voltage range. In CMOS circuits of the type that will be described, a down level representing (arbitrarily) a logical 0, is commonly in the range of 0 to 0.3 volts and an up level is in the range of 4.7 to 5 volts. The corresponding TTL logic levels are typically 0 to 0.8 volts and 2.4 to 6.5 volts. These specific voltage ranges will help to explain the circuit of this invention, but the problem that has been described can exist occur with other voltage ranges and the specific circuit that will be described later will be useful in a variety of applications.
Circuits that make this voltage change are commonly called TTL input buffer circuits. The buffer circuit of this invention uses a feature of many TTL input buffers: it has an input inverter stage that receives the TTL level signals and an output inverter stage that provides signals at CMOS voltage levels for associated CMOS circuits.
These inverter circuits are well known, but it will be helpful to review the features and terminology that particularly apply to this invention. They have two FET's that are each connected to conduct between opposite ones of the power supply terminals and a common output node. It will be convenient to call one of these FET's the upper FET and the other one the lower FET according to their usual location in a circuit diagram. The two FET's are complementary (one has an n-channel and the other has a p-channel) and they switch oppositely in response to an input signal at the common connection of their gate terminals. When the input signal is up, the lower FET turns on and the upper FET turns off; when the input is down the lower FET turns off and the upper FET turns on.
When an inverter of this type is used as an input buffer for TTL signals, the up level from the TTL circuits may be high enough to turn on the lower FET but not high enough to turn off the upper FET. If both FET's are on together, they dissipate an undesirably high level of power.
3. THE PRIOR ART
IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, Apr. 1990, pages 525-530, on page 526 discusses the problem of interconnecting TTL circuits and CMOS circuits. FIG. 4 on page 527 shows a buffer circuit with two inverter stages. An FET Q10 is connected between the source of the upper FET, Q9, of the input stage and the corresponding power supply point. The gate of Q10 is connected to a reference potential point established by the circuit in the dashed line box to the left and it limits the current in the input inverter stage.